The basic operation of a static random access memory (SRAM) array is typically divided into evaluation time and restore time. The proper operation of the SRAM memory requires that sufficient time be allotted to the evaluation time. In practice, this time is related to the time the wordline (WL) is active. The evaluation and restore time are determined by the specific circuits implemented in the memory array. The behavior exhibited by the SRAM cell differs greatly across different PVT corners. This requires adaptation of the evaluation time accordingly for the different PVT corners.
Digital circuitry, however, does not typically allow proper tracking due to the special nature of the SRAM cell combined with the fact that its behavior does not track well with regular logic behaviors due to the small device sizes of the SRAM cell components. Significant errors in tracking of the restore signal are likely to lead to functional failure due to the SRAM cell not being able to fully evaluate cell contents in the given time. For example, as the supply voltage decreases, the required evaluation time increases in order to allow the bitline (BL) to discharge, which is now lengthened due to the drop in supply voltage. In such cases, the WL pulse width is typically not sufficient to read the cell. This can be seen in the graph shown in FIG. 3A for example.
The evaluation process in practice is sensitive to PVT variations. In particular, the passgate transistor of the typically SRAM memory cell is very sensitive to changes in gate voltage. Changes in the threshold voltage also affect the operation with a key problem being threshold voltage mismatch in the array.
To solve this problem, one prior art solution uses digital delay chains to produce the required amount of delay. This solution, however, does not track SRAM behavior well especially in extreme PVT corners.
Another prior art solution attempts to mimic the array access path using a dummy bit line. In this method a “dummy” column of cells are used that produces an SRAM like delay. This, however, adds complexity to the SRAM core as you cannot have a standalone column of cells due to printability issues. Further, yields may suffer due to the relatively small SRAM cell features.
Yet another prior art solution is to drive the restore (i.e. the evaluation end) from the mid cycle clock edge. This, however, usually enforces very high hold requirements as the evaluation pulse width is very wide. It requires a slow frequency or special duty cycle and is sensitive to clock jitter.
There is thus a need to improve the restore tracking to cover variations in PVT including PVT corners that does not suffer from the disadvantages of prior art solutions discussed above.